index.md (1266B)
1 +++ 2 title = 'Superscalar operation' 3 +++ 4 # Superscalar operation 5 for a pipelined processor, the maximum throughput is one instruction per clock cycle 6 7 equip a processor with multiple execution units, each of which is pipelined, and it can handle several instructions in parallel 8 9 the processor is multiple-issue — several instructions execute in same clock cycle but different execution units 10 11 can achieve throughput of more than one instruction per cycle — superscalar processors 12 13 the fetch unit can get two or more instructions per cycle and put them in an instruction queue 14 15 a dispatch unit takes two or more instructions from front of queue, decodes them, and sends them to execution units 16 17 superscalar processor with two execution units: 18 19  20 21 instruction flow in this processor: 22 23  24 25 this leads to out-of-order execution, so results have to be saved in temporary registers 26 27 the temporary registers assume the role of the permanent registers and store the result of the instruction 28 29 the commitment unit guarantees in-order commitment using a reorder buffer (queue) 30 31 when an instruction reaches the head of the queue, the data is transferred from a temporary register to a permanent register